Unless otherwise indicated herein, the materials described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
As more and more cores become integrated into a single multicore chip, thread migration may be increasingly utilized in order to manage and improve functionality, performance, and/or temperature of the multicore chip. In a typical thread migration scenario, a first core may execute a thread and utilize a first cache. As the first core executes the thread, the first cache may fill with requested data retrieved from memory. After the first cache fills, the first cache may yield cache hits whereby the first core can efficiently retrieve the requested data from the first cache.
During a thread migration, a controller may migrate the thread from the first core to a second core such that the second core takes over execution of the thread. The second core may utilize a second cache that is “cold” (i.e., empty). As a result, the second cache may yield, instead of cache hits, cache misses whereby the requested data is not found in the second cache. After each cache miss, the requested data may be fetched on-demand from another cache, such as the first cache, on the multicore chip. When the second cache “warms up” (i.e., fills with the requested data), the second cache may experience cache hits. However, warming up the second cache through on-demand fetching can incur significant time and energy costs. Such costs can be especially burdensome when filling large caches and in architectures implementing frequent thread migration.